library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decoder_7dp is
port(num1:in integer;display1: out std_logic_vector(6 downto 0);
		num2:in integer;display2: out std_logic_vector(6 downto 0));
end entity decoder_7dp;

architecture digitalpipe of decoder_7dp is
begin
p1:process (num1,num2)
begin
	case num1 is
		when 0 => 
			display1<= "1000000";
		when 1 => 
			display1<= "1111001";
		when 2 => 
			display1<= "0100100";
		when 3 => 
			display1<= "0110000";
		when 4 => 
			display1<= "0011001";
		when 5 => 
			display1<= "0010010";
		when 6 => 
			display1<= "0000010";
		when 7 =>
			display1<= "1111000";
		when 8 => 
			display1<= "0000000";
		when 9 => 
			display1<= "0010000";
		when others=> 
			display1<="-------";
	end case;
	case num2 is
		when 0 => 
			display2<= "1000000";
		when 1 => 
			display2<= "1111001";
		when 2 => 
			display2<= "0100100";
		when 3 => 
			display2<= "0110000";
		when 4 => 
			display2<= "0011001";
		when 5 => 
			display2<= "0010010";
		when 6 => 
			display2<= "0000010";
		when 7 =>
			display2<= "1111000";
		when 8 => 
			display2<= "0000000";
		when 9 => 
			display2<= "0010000";
		when others=> 
			display2<="-------";
	end case;
	end process p1;
end architecture digitalpipe;